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Flexible static memory controller (FSMC)
Figure 174. Synchronous multiplexed write mode - PSRAM (CRAM)
Memory transaction = burst of 4 half words
HCLK
CLK
RM0008
A[25:16]
NEx
NOE
Hi-Z
addr[25:16]
NWE
NADV
NWAIT
(WAITCFG = 0)
DATALAT CLK cycles
inserted wait state
A/D[15:0]
Addr[15:0]
data
data
data
data
1 CLK 1 CLK
cycle
cycle
ai14731c
1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
434/995
Doc ID 13902 Rev 9
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